This invention relates to editing packets for fast serial interfaces and more specifically a method for easily confirming corresponding relationships between an edited packet and the serial data derived from the edited packet
PCI Express has become popular as an interface that enables faster data communication. It adopts packed-based protocol and serial communication as an electrical interface. FIG. 1 shows a structure of PCI Express 12. A PCI Express software layer 10 has compatibility with legacy PCI software, and software working on PCI, e.g. drivers and the like, works in a system using PCI Express. In creating transmission data, a transaction layer 14 receives data from the software layer 10 and generates a transaction layer packet (TLP) that is provided to a data link layer 16. The data link layer 16 adds a data link packet (DLLP) to the TLP and provides it to a physical layer 18. The physical layer 18 adds a physical layer packet (ordered sets) and converts the combined packets into electrical signals for transfer. A mechanical layer 19, such as an electrical socket, circuit board traces and the like, is provided as a mechanical structure depending on an application. In case of receiving data, the flow of the processes is in reverse, i.e. the physical layer receives an electrical signal from a mechanical layer and converts it into a packet that is provided to the transaction layer via the date link layer. As described, each layer communicates the packet with the corresponding layer of the communication device.
FIG. 2 shows a structure of a complete PCI Express packet wherein sub-packets are gradually added to the outsides as it advances layer by layer from the transaction layer to the physical layer. ECRC (End to end CRC), also called as TLP Digest, is optionally added in the transaction layer and used for determining whether there is an error of the TLP with CRC (Cyclic Redundancy Check). The data link layer adds LCRC (Link CRC) to assure reliability of the TLP that is used to detect an error. If an error is detected, the TLP may be re-transmitted to recover the error. A sequence number is a serial number of the packet. The receiving side detects duplication or lack of the TLP using the sequence number. The physical layer adds K characters (control codes), SDP (Start of DLLP) or STP (Start of TLP), to the packet from the data link layer as a starting marker (start frame) at the beginning of the packet. It also adds “END” character as an end frame at the end of the packet.
FIG. 3 is an exemplary block diagram of the physical layer that has transmitter and receiver sides. The transmitter side has a Tx buffer 20 that receives the packet from the data link layer. A multiplexer 24 adds the K characters to the packet. The byte striping 26 distributes the data depending on the number of lanes. Scramblers 28 may be liner feedback shift registers (LFSRs) that randomizes the data pattern according to an equation of G(X)=X16+X5+X4+X3+1. This is for preventing EMI (electromagnetic interference) that may be concentrated at a particular frequency. The scramblers 28 scramble D characters included in the TLP and DLLP but not K characters so that a receiving device may easily recognize the K characters.
8b/10b encoders 30 uses conversion tables to convert 8 bit data patterns into 10 bit data patterns wherein the encoded 10 bit data patterns have no more than five 1 s or 0 s in a row. The shorter series of 1 or 0 cycles makes it easier to recover a clock from the data at the receiver side. Note that the PCI Express specification calls 8 bit data before encoding a “Character” and 10 bit data after encoding a “Symbol”.
Parallel to serial converters 32 convert the 10 bit data from the 8b/10b encoders 30 into serial data according to a Tx clock. The serial data is provided as differential electric signals from Tx drivers 34. Each lane has four transmission lines of two transmitter lines and two receiver lines. In the transmitter line, higher frequency components are attenuated more than lower frequency components. Then, the output electric signals from the driver 34 are de-emphasized for reducing errors during the transmission.
At the receiver side, receivers 40 receive the differential signals and clock recovery circuits 42 recover clocks (i.e. Tx clocks) from the received signals. Buffers 44 extract data from the differential signals according to the recovered clocks, and provide it to serial to parallel converters 46 according to an Rx clock of the receiver side. Most of the following processes are reverse version of the transmitter side of the physical layer described above.
A signal generator is an apparatus that can store digital waveform data in the storage device such as a memory, hard disk drive (HDD), etc. The digital waveform data is converted analog signal output. The digital waveform data may be previously stored data defined in the PCI Express standards or use defined digital waveform data. One application for a signal generator is in developing a new electronic apparatus. The signal generator may provide an expected output signal from an uncompleted circuit block of the apparatus to a circuit block following the uncompleted circuit block to confirm whether the following circuit block works as expects. Another application is a durability test against jitter or distortions where the signal generator provides a signal including intentional jitter or distortions to a circuit under test. Further, the signal generator may be used for measuring characteristics of a fast serial interface such as PCI Express, etc. The signal generator provides a signal having waveform patterns suitable for the characteristic testing and an oscilloscope is used to receive an output from the transmission lines to measure the characteristics with eye pattern display, etc. AWG7000B series signal generators, manufactured and sold by Tektronix, Inc., Beaverton, Oreg., are such signal generators.
FIG. 4 is an exemplary block diagram of a signal generator. A CPU (Central Processing Unit) 70 controls the signal generator system according to programs stored in a hard disk drive (HDD) 74. The HDD 74 may also be used for storing large amounts of data, such as waveform generation software, digital waveform data and the like. A memory 72, such as RAM memory, is used for a work area for the CPU 70 to read programs from the storage device. A user can set up the signal generator via an operation panel 84 that includes keys, knobs, and the like. A display 82 provides visual information relating to signal patterns and user settings. An external display output circuit 80 provides a video output which may be connected to an external display 94 for providing a larger display area in addition to the built-in display 82 of the signal generator. A signal generation circuit 76 generates signal patterns based on user defined parameters. In this example, it has two channel outputs and inputs for trigger and event signals. Receipt of these signals enables conditional actions. An input/output port 88 is used for connecting an external keyboard 90, a pointing device 92, such as a mouse, and the like to the signal generator. The external keyboard 90 and/or pointing device 92 may be included as parts of the operation means of the signal generator. These blocks are coupled together via a bus 78. A LAN (Local Area Network) interface may be connected to the bus 78 to couple the signal generator to an external PC 96. The external PC 96 allows a user to remotely control the signal generator as desired.
A waveform of an electric signal that the user desires is stored in the memory or HDD as waveform data. The waveform data may be edited with waveform editing software working on a PC as is known. ArbExpress, manufactured and sold by Tektronix, Inc. is such a waveform editing software. U.S. Application Publication 2008/0313516 discloses waveform data edit with waveform editing software.
It would be convenient for measuring characteristics or performing compliance testing of a PCI Express receiver if a signal generator provides differential signals that replicate the signal outputs of the transmitter drivers of the physical layer of PCI Express transmitter. The signal generator can easily generate arbitrary signals having different patterns and intentional jitter, and provide them according to a programmed sequence.
FIG. 5 shows a screen display of table for use in packet editing. The table may be displayed on a display screen of the display device 82 of the signal generator. A user may edit the packet using the operation panel 84, keyboard 90, mouse 92, for example. A “Label” column shows the elements of the packet. The user may input names of packet files that the user wants to set to the respective elements in a “Block/Sub Sequence” column. The packet files may be previously stored in a library and the user may select desired packet files from the library. Some of the packet files are defined by the specification but the user may revise the files prepared in the library. A “Repeat” column is used to designate the number of times the packet file data repeats. A “Go To” column is used to designate where to jump following the packet file data.
The signal generator generates electric signals representative of the user defined packets. The electrical signals are coupled to transmission lines of the PCI Express with the signals at the output of the transmission lines being observed using an oscilloscope displaying eye patterns. This allows measuring characteristics of the transmission lines when various signal patterns are provided.
It is not easy for the user to confirm relationship between the packet and the output serial pattern when the table format as shown in FIG. 5 is used for editing the packet. If an error occurs in the serial pattern, it would be difficult to identify which element of the packet causes the error. Therefore, what is desired is to provide a way to easily confirm the relationship between an edited packet and the actual output packet data derived from the edited packet.